Bonding defects such as dangling bonds existing on grain boundaries of polycrystalline silicon included in active channel region are known to function as a trap for an electric charge carrier during fabrication of a thin film transistor (hereinafter referred to as “TFT”) using polycrystalline silicon.
Therefore, the size of grains, uniformity of grain size, number and position of the grains and the direction of the grains may not only have a fatal effect on TFT characteristics directly and/or indirectly, such as threshold voltage (Vth), subthreshold slope, charge carrier mobility, leakage current and device stability, but may also have a fatal effect on TFT uniformity according to position of the grains when fabricating an active matrix display substrate using TFT.
The number of fatal grain boundaries (hereinafter referred to as “primary” grain boundaries) included in the active channel regions of TFT all over the substrate of the display device can be equalized or varied according to size of grains, inclination angle θ of the grains, dimension of the active channel (length (L) and width (W)) and the position of each TFT on the substrate (see, for example, FIG. 1A and FIG. 1B).
As illustrated in FIG. 1A and FIG. 1B, the number of “primary” grain boundaries included in the active channel regions for grain size Gs, active channel dimension L×W and inclination angle θ of the grains (that is, the number of “primary” grain boundaries included in the active channel regions according to position of TFT substrate or display device) is Nmax (3 in case of FIG. 1A) or Nmax-1 (2 in case of FIG. 1B) when the maximum number of grain boundaries is Nmax. More uniformity in the TFT characteristics may be secured when the number of “primary” grain boundaries of Nmax for all TFTs is included in active channel regions. That is, the more each TFT has an equal number of grain boundaries, the more uniformity the device obtains.
On the other hand, it may be understood that uniformity is worse in characteristics of TFTs on TFT substrates or display devices if the number of TFT including Nmax “primary” grain boundaries is equal to the number of TFT including Nmax-1 “primary” grain boundaries.
Polycrystalline or single crystalline grains may be capable of forming large silicon grains on a substrate using sequential lateral solidification (SLS) crystallization technology (FIG. 2A and FIG. 2B). Characteristics similar to characteristics of TFT fabricated of single crystalline silicon may be obtained when fabricating TFT using the large silicon grains. However, a plurality of TFTs for driver and pixel array should be fabricated for an active matrix display.
For example, approximately one million pixels are made in fabricating an active matrix display having SVGA resolution. One TFT may be required in each pixel in the case of liquid crystal display (LCD). At least two or more TFTs may be required in a display using organic light emitting materials such as organic electroluminescent device.
Therefore, it may be difficult to fabricate an active matrix display by growing a certain number of grains to a certain direction only in the active channel regions of each of more than one million or two million TFTs.
A technology for converting the amorphous silicon on the whole substrate into polycrystalline silicon, or for crystallizing selected regions only on the substrate using SLS technology after depositing amorphous silicon by PECVD, LPCVD or sputtering is disclosed in U.S. Pat. No. 6,322,625 as illustrated in FIG. 2A and FIG. 2B.
The selected region is also quite a large region compared to an active channel region having dimension of several μm by several μm. Furthermore, the size of the laser beam used in crystallization technology is approximately several mm×scores of mm. Stepping and shifting of the laser beam or stage are required to crystallize the amorphous silicon of the whole region or a selected region on substrate, where misalignment exists between regions on which the laser beam is irradiated. Misalignment may be included in active channel regions of a plurality of TFTs. The number of grain boundaries vary, and TFT on the whole substrate or in the driver region or the pixel cell region may have unpredictable non-uniformity. The non-uniformity may have a fatal effect on an active matrix display device.
Fabricating TFTs for an LCD device comprising a driver and pixel array by forming large silicon grains using SLS crystallization technology is disclosed in U.S. Pat. No. 6,177,391. Barrier effects of grain boundaries for the electric charge carrier direction may be minimized, as illustrated in FIG. 3A, so that the large silicon grains obtain TFT characteristics next to those of single crystalline when the direction of the active channels is parallel to direction of grains grown by a SLS crystallization method. Many grain boundaries in which TFT characteristics function as trap of electric charge carrier, also exist such that TFT characteristics may deteriorate, as illustrated in FIG. 3B.
Practically, there are cases that a TFT inside the driver circuit and a TFT inside the pixel cell regions generally have an angle of 90° when fabricating an active matrix display, wherein uniformity of the device can be improved by fabricating the active matrix display in such a way that the direction of the active channel regions is inclined to grain growing in a direction at an angle of 30 to 60°, so that uniform characteristics between TFTs are improved and characteristics of each TFT do not greatly deteriorate (FIG. 3C).
However, it is likely that fatal grain boundaries are included in active channel regions since limited sized grains formed by SLS crystallization technology are also used in this method. Therefore, there is a problem that unpredictable non-uniformity causing a difference in characteristics between TFTs exists in this method.
On the other hand, a polycrystalline silicon thin film consists of transistors to be used as a switching device or a driving device for pixels in a flat panel display device, such as an organic electroluminescent display device or a liquid display device, wherein an active driving type active matrix organic electroluminescent display device comprises at least two thin film transistors for each sub-pixel.
An organic electroluminescent device comprises an emission layer formed of an organic matter between an anode electrode and a cathode electrode. In the organic electroluminescent device, holes injected from the anode electrode are moved to the emission layer via a hole transport layer as anode and cathode voltages are being applied to the respective electrodes. Electrons are injected into the emission layer from the cathode electrode via an electron transport layer so that the electrons and holes are reunited with each other in the emission layer to produce exitons, and light emitting materials of the emission layer are emitted to form a picture as the exitons are being changed from the excited state to the ground state. A full color organic electroluminescent display device comprises pixels emitting the colors red (R), green (G) and blue (B) in order to realize full colors.
However, the emission efficiency (Cd/A) of each emission layer of red, green and blue for emitting each color varies by color in the organic electroluminescent display device. Furthermore, it is difficult to obtain an appropriate degree of color balance, or white balance as some colors have lower luminance while other colors have higher luminance. This may occur even when an equal current is applied to the sub-pixel since luminance of the emission layer is approximately proportional to the current values applied to each sub-pixel.
For example, a corresponding amount of additional current should flow to the red and blue emission layers to adjust white balance, since the emission efficiency of the green emission layer is three to six times higher than the emission efficiency of the red emission layer and the blue emission layer.
On the other hand, a method for applying different voltages supplied through a driving line, that is, a driving voltage (Vdd) to each pixel, is disclosed in Japanese Patent Laid-open Publication No. Heisei 5-107561 as a conventional method for adjusting white balance.
Furthermore, a method for adjusting white balance by controlling the size of the driving TFT is disclosed in Japanese Patent Laid-open Publication No. 2001-109399. The amount of current flowing to respective red, green and blue organic electroluminescent devices is controlled by differently designing W/L values for each red, green and blue pixel where the channel width is W and the channel length is L in the channel regions of the driving TFT.
A method for adjusting the white balance by forming different sized pixels is disclosed in Japanese Patent Laid-open Publication No. 2001-290441. The white balance and a long life cycle may be enabled by forming the green color emitting region in such a way that the emission area of the green color emitting region having the highest emission efficiency is the smallest compared to the emission area of the red color and the blue color emitting regions. This emission efficiency difference can be enabled by the area of the anode electrode.
Additionally, one method for controlling luminance varies the voltage range applied through data lines for each red, green and blue pixel, thereby controlling the current amount.
However, the foregoing methods do not consider the crystal structure of the polycrystalline silicon in a TFT of a flat panel display device using polycrystalline silicon. Current mobility can be varied according to the crystal state of the polycrystalline silicon included in the active channel regions of TFT. Even in this case, the white balance may not be adjusted.
Furthermore, a flat panel display device is driven by generally using complementary metal oxide semiconductor thin film transistor (CMOS TFT) in constructing circuits in the flat panel display device.
However, an absolute value of the threshold voltage of a TFT is generally larger than an absolute value of the threshold voltage of a MOS transistor using a single crystalline semiconductor. Furthermore, an absolute value of the threshold voltage of an N type thin film transistor is quite different from an absolute value of the threshold of a P type thin film transistor. For example, if the threshold voltage of the N type thin film transistor is 2 V, the threshold of the P type thin film transistor may be −4 V.
Therefore, a great threshold voltage absolute value difference between the P type thin film transistor and N type thin film transistor may not be desirable in operating circuits, and it may function as a barrier in reducing the driving voltage. For example, typically, a P type thin film transistor having a large threshold voltage absolute value not properly operated at a lower driving voltage.
That is, the P type thin film transistor generally functions only as a passive element, such as a resistor, and is not operated fast enough. It may be necessary to increase the driving voltage to operate the P type thin film transistor just as a passive element.
Particularly, a difference in the work function between the gate electrode and the intrinsic silicon semiconductor may be decreased as much as −0.6 eV in the case where the gate electrode is formed of a material having a work function of 5 eV or less, such as aluminum. Consequently, the threshold voltage of the P type thin film transistor is shifted to a negative value while threshold voltage of the N type thin film transistor approaches a zero voltage. Therefore, the N type thin film transistor generally becomes the on-state.
In the above state, it is desirable that the threshold voltage absolute value of the N type thin film transistor be almost equal to that of the P type thin film transistor. The threshold voltage has been controlled by doping N type or P type impurities at a very low concentration of 1018 atoms/cm3 or less. That is, the threshold voltage has been controlled to about 0.1 V or less by doping impurities having a concentration of 1015 to 1018 atoms/cm3.
However, a shift of the threshold voltage may not observed even if impurities are added to the semiconductor in a concentration of 1018 atoms/cm3 or less when using a semiconductor that is not a single crystalline semiconductor. Furthermore, the threshold voltage is rapidly changed, and the conductivity becomes p-type or n-type if the concentration of impurities is 1018 atoms/cm3 or more, since the polycrystalline silicon has many defects. The added impurities are trapped and can not be activated by the defects since the defect concentration is 1018 atoms/cm3. Furthermore, the concentration of the impurities is larger than the concentration of the defects, excess impurities are activated, and the conductive type is changed to n or p type.
In order to solve these problems, the length of the channels is varied so that the channel length of a P type thin film transistor is shorter than that of an N type thin film transistor, such as described in U.S. Pat. Nos. 6,492,268, 6,124,603 and 5,615,935. However, these patents also have problems in that the manufacturing process is complicated, since the channels are manufactured in such a way that length of the channels is different.